High speed digital level shifter

ABSTRACT

A high-speed digital level shifter is described. The preferred embodiment shifts an input signal with a lower amplitude to a signal with a higher amplitude. The level shifter includes a signal driver circuit to drive up the input signal to a driver signal having higher voltages. The driver signal is used to drive an output circuit that generates an output signal having amplitude of a high voltage power source. The output circuit has improved performance being driven by the driver input signal. A signal stepper is added to further improve the performance by pulling up the output voltage in two stages.

TECHNICAL FIELD

This invention relates generally to digital circuits, and morespecifically to digital level shifters.

BACKGROUND

A level shifter is a circuit that converts an input signal having thevoltage amplitude of VDD₁ into an output signal having the voltageamplitude of VDD₂. Typically, the amplitude is converted by fixing thelower potential side, typically referred to as VSS, and converting thepotential at the higher potential side. Level shifters are widely usedin integrated circuits where more than one application circuit, eachhaving different amplitudes, are integrated together.

A common application is shifting the voltage of a signal transferredbetween an input/output (“IO”) circuit and a core circuit. Historically,the IO operation voltage was compatible with the core operation voltage.However, with the shrinking of the VLSI circuit, the operation voltageof the core circuit continues to be reduced while the IO operationvoltage stays relatively steady, so that currently, the core operationvoltage is typically much lower than the IO operation voltage. Forexample, in deep sub-micron technology, the core operation voltage hasdropped to about 0.9 to 1V, and the IO operation voltage stays at about2.5V to 3.3V. Therefore a signal needs to be level shifted before it issent from a core circuit to an IO circuit or from an 10 circuit to acore circuit. Usually, VSS is set at ground potential or 0V, and VDD isset at 0.9 to 1V for the core and 2.5 to 3.3V for the IO. In otherinstances, VSS may be set to a higher voltage level or a negativevoltage level. In such cases, only the level of VDD need be adjusted. Inother instances, the level of VSS is adjusted, or the levels of both VSSand VDD are adjusted.

FIG. 1 illustrates a conventional digital level shifter circuit. Nodes 2are power supply nodes at a power supply voltage VDD, which is a coreoperation voltage. Nodes 26 are power supply nodes at a power voltageVDDH, which is an IO operation voltage and is higher than VDD. Node 12is an input node and node 30 is an output node. When the input signal atnode 12 switches from 0 (0 volt) to 1 (VDD), the voltage at node 14changes from VDD to 0V since pMOS 4 and RMOS 8 form an inverter. Thegate voltage of the transistor 20 at node 28 also changes to 0 volt,causing the nMOS transistor 20 to cut off. The pMOS transistor 6 andnMOS transistor 10 form another inverter, so that the voltage at node 16changes to VDD, causing transistor 18 to conduct. The voltage at node 32is pulled down so that pMOS transistor 24 conducts. The output voltageat node 30 is pulled up to VDDH by transistor 24.

If input signal at node 12 switches from 1 to 0, voltage at node 14changes to 1, causing transistor 20 to conduct and the output voltage atnode 30 is pulled down. Simultaneously, the voltage at node 16 switchesto 0V, causing transistor 18 to cut off, and the voltage at node 32 ispulled up by the pMOS transistor 22. Transistor 24 is cut off due to thehigh gate voltage at node 32, and the voltage at output node 30 iseventually pulled down to 0 volt. Therefore, the input signal withamplitude of VDD is shifted to an output signal with amplitude of VDDH.

The circuit illustrated in FIG. 1 performs well when VDD is higher thanthe threshold voltage of the transistor 18 and 20 with adequate margin.However, when a VLSI circuit gets smaller, the gate oxide of the coreCMOS gets thinner. The supply voltage of the core CMOS is also loweredto protect the gate oxide from damage and the hot carrier effect. WhenVDD is dropped to a level close to the threshold voltage of nMOS 18 and20, the conventional low-to-high level shifter becomes slow. To explainin detail, assume the input voltage at node 12 is VDD, so thattransistors 20 and 22 are off and transistors 18 and 24 are on. When theinput voltage at node 12 is switched to 0V, the state of the transistor20 changes from off to on so that it starts to pull down the voltage atnode 30. The drain current of a transistor can be expressed as:I _(d) =k*[2(V _(gs) −V _(t))V _(ds) −V _(ds) ²]  [Eq. 1]where k is a device parameter, I_(d) is the drain saturation current ofthe transistor, V_(gs) is the voltage difference between the gate andsource, and V_(t) is the threshold voltage of the transistor. It isobserved that the current is directly related to V_(gs)−V_(t). If thevoltage VDD at node 28 is close to V_(t), the drain-source current I_(d)is very small, and it is hard for transistor 20 to pull down the outputvoltage at node 30, so that the level shifter is slow and high frequencyresponse is degraded. One of the common solutions is to increase theaspect ratio W/L to increase the transistor 20's drain-source current.This is because k can be expressed as:k=½μ _(n) C _(ox)(W/L)  [Eq. 2]where μ_(n) is the electron mobility, C_(ox) is the capacitance per unitarea of the capacitor between the gate electrode and the channel, W isthe channel width, L is the channel length, and W/L is the gate aspectratio. When W/L increases, k increases and the I_(d) increases. When thecore circuit's operation voltage continues to drop, W/L needs to befurther increased to compensate.

Since power supply voltage VDDH stays higher, the transistors 18, 20, 22and 24 are normally thick oxide transistors so that they can withstandhigher operation voltages without being damaged. However, the thickoxide transistors also have higher threshold voltages, making thethreshold voltage closer to VDD. If the VDD is equal to or lower thanthe threshold voltage of transistors 18 and 20, the transistors cannotbe turned on, so that the level shifter will malfunction. Therefore,there is the need for a level shifter that has high performance evenwhen operated at a very low core operation voltage.

SUMMARY OF THE INVENTION

A high-speed digital level shifter is described. The preferredembodiments can shift an input signal with lower amplitude VDD to asignal with higher amplitude VDDH. The preferred embodiments include asignal driver circuit to drive up the input signal to a driver signalhaving higher voltages. The driver signal is used to drive an outputcircuit that generates an output signal having amplitude of VDDH. Theperformance of the output circuit is improved since the driver signal ishigher. A signal stepper is added to further improve the performance bypulling up the output voltage in a two-stage process.

In one aspect of the preferred embodiment, the driver circuit isimplemented using charge pumps. The driver circuit drives up an inputsignal in a range between 0V and VDD to a driver signal in a rangebetween (VDD−V_(th)) and (2VDD−V_(th)). The signal stepper isimplemented using two inverters. When the input signal switches from 0to 1, the output is pulled to a voltage close to VDD through a passgate, then pulled up to VDDH. The design of the preferred embodiment ofthe present invention is simple and implementation is easy.

The frequency response of the preferred embodiments of the presentinvention is improved over the prior art. The preferred embodiment workswell for 1.25 Gbps signals, and it can be used for deep sub microntechnology.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and theadvantages thereof, reference is now made to the following descriptionstaken in conjunction with the accompanying drawings, in which:

FIG. 1 illustrates a conventional level shifter;

FIG. 2 is a schematic diagram of a preferred embodiment;

FIG. 3 illustrates a schematic view of a simplified charge pump;

FIG. 4 is an implementation of a preferred embodiment using chargepumps; and

FIG. 5 illustrates the voltages at different nodes of a preferredembodiment as a function of time.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the presently preferred embodiments arediscussed in detail below. It should be appreciated, however, that thepresent invention provides many applicable inventive concepts that canbe embodied in a wide variety of specific contexts. The specificembodiments discussed are merely illustrative of specific ways to makeand use the invention, and do not limit the scope of the invention.

The preferred embodiments are illustrated in FIGS. 2 through 5, whereinlike reference numbers are used to designate like elements throughoutthe various views and illustrative embodiments of the present invention.It is to be appreciated that for simplicity, it is assumed that theinput signal switches between 0V and VDD, and the VSS of the circuit is0V. Those skilled in the art will appreciate that different values maybe used.

FIG. 2 illustrates a preferred embodiment of the present invention. Anoutput circuit is used to generate an output signal. The output circuitis formed of a symmetrical pair of pMOS transistors 82, 84 and a pair ofnMOS transistors 78 and 80. A signal driver 50 is used to drive up theinput signal voltage. The input signal, as is conventional, consists ofa logical pair of voltage levels, i.e., logical low and logical high. Inthe illustrated embodiments, a logical low is about 0V and a logicalhigh is about the VDD voltage level for a core device (e.g., 1V). Theoutput signal also consists of a logical pair of voltage levels, logicallow and logical high, and in the illustrated embodiment, the logical lowat the output is about 0V and the logical high at the output is aboutthe VDDH (e.g., 3.3V) for an IO device.

As will be explained in greater detail below, the low voltage of theinput signal is boosted to voltage V_(low). The high voltage of theinput signal is boosted to voltage V_(high), where V_(high) ispreferably higher than VDD and also higher than the threshold voltage ofthe transistors 78 and 80. The un-inverted boosted output of the signaldriver 50 is coupled to the gate of transistor 78 and the invertedboosted output of signal driver 50 is coupled to the gate of transistor80. Since the output (whether inverted or un-inverted) of the signaldriver 50 is higher than VDD, the V_(gs) of transistors 78 and 80,respectively, are higher, so their respective drain-source current isincreased. This allows for faster switching of the output node 90.

To further improve the performance of the level shifter, a voltagestepper 52 is added to increase the speed at which either output node 90or its counterpart node 92 is changed from 0V to VDDH. The voltagestepper 52 is coupled to the input signal at node 72 so that its output(or more accurately its two outputs, one of which is simply the inverseof the other) is also controlled by the input signal. The function ofvoltage stepper 52 can be explained briefly as follows. When inputvoltage V_(in) at node 72 switches from 0V to VDD, transistor 80switches from on to off, because its gate voltage (at node 88) is drivenlow by the inverted output from signal driver 50. Likewise, thenon-inverted output from signal driver 50 turns on transistor 78, henceturning on gate 84. Voltage V_(out) at node 90 is brought “high,” i.e.,from about 0V to about VDDH (less the voltage drop across transistor84). The process whereby transistor 84 pulls output node 90 high can bedivided conceptually into an initial stage and a final stage. In theinitial stage, where the gate of transistor 84 is first transitioningfrom high to low, the drain-source current is small. In the final stage,as the gate voltage of transistor 84 reaches its logical low level,transistor 84 is fully turned on and its drain-source current is high,thus pulling output node 90 to its logical high level more quickly. Inother words, at high operation frequencies, the switching speed oftransistor 84 (or of transistor 82 when switching from high to low), cansignificantly impact the speed at which the output node 90 can switch.

Output node switching speed can be enhanced by the use of voltagestepper 52 by in effect “pushing” the output node to an intermediatevoltage level (i.e., intermediate the logical low voltage of e.g., 0Vand the logical high voltage level of e.g., VDDH) during the initialstage while transistor 84 is turning on. This “pushing” effect isaccomplished by transistor 80 which acts as a pass gate, also known as asource follower because the drain voltage follows its source voltage. Assource follower transistor 80 is transitioning from its on state to itsoff state, its source (node 76) is driven high by voltage stepper 52.The drain of transistor 80 (which is at output node 90) follows thesource voltage, so the drain voltage/output voltage is “pushed” to ahigher voltage by transistor 80. At some point, pull-up transistor 84turns on fully (i.e., the final stage discussed above) and transistor 80turns off fully. At this point, output voltage node 90 is at someintermediate voltage (between 0V and VDDH), and transistor 84 need onlypull the output node up the remainder of the way to its high level. Thissignificantly increases the switching speed.

The preferred embodiment illustrated in FIG. 2 provides two advantageousfeatures. The first advantageous feature is that signal driver 50increases the voltage level to the gates of output stage transistors 78and 80, thus ensuring that the gate voltage is above the thresholdvoltage and increasing the drain-source current. The increaseddrain-source current allows transistor 78 to more rapidly pull node 92low and transistor 80 to more rapidly pull node 90 low. Secondly,voltage stepper 52 drives the source of output state transistors 78 and80, respectively, high during switching, thus driving node 90 or 92,respectively, to an intermediate voltage state above 0V (logical low)during the transition of node 90 or 92 from a logical low to a logicalhigh state. This allows pull-up transistor 84 or 82, respectively, topull node 90 or 92, respectively, to the logical high state morequickly.

One skilled in the are will recognize that signal driver 50 and voltagestepper 52 can be implemented in various ways. One preferred embodimentis illustrated in FIG. 4. The preferred embodiment uses charge pumps todrive up the gate to source voltage, V_(gs), of transistors 78 and 80,respectively, so that the drain-source current is increased. A chargepump is a circuit that generates a voltage higher than the supplyvoltage from which it operates. With a proper design, a charge pump cangenerate a voltage multiple times higher than the power supply voltage.Normally, to obtain a voltage multiple times higher than the powersupply voltage, multiple stages are used to pump the voltage higher andhigher until the desired voltage is reached.

FIG. 3 illustrates a simplified one-stage charge pump used in thepreferred embodiment. Node 40 is the input signal node, and the inputsignal switches between 0V and VDD. Node 42 is the output node withvoltage V_(out). The power supply at node 46 has a supply voltage VDD.Switch 44 has two phases, closed and open. During the first phase,switch 44 is closed so that the capacitor 48 is charged, and the chargeQ equals VDD*C, where C is the capacitance of the capacitor 48. Duringthe second phase, the switch 44 is opened, and the voltage V_(in) of theinput signal is switched to VDD. Since the charge stored in thecapacitor is a constant, there is:(V _(out) −V _(in))*C=VDD*C  [Eq. 3]orV _(out) =VDD+V _(in)  [Eq. 4]In the case when V_(in) equals VDD, V_(out) equals 2VDD. When V_(in)switches between 0V and VDD, V_(out) switches between VDD and 2VDD.

FIG. 4 illustrates a preferred embodiment using the charge pump. Nodes62 are connected to a power supply with a lower supply voltage VDD.Nodes 86 are connected to a power supply with higher voltage VDDH, whichis higher than VDD. The signal driver 50 is implemented using capacitors96, 98, and NMOS transistors 100 and 102. Preferably, capacitors 96 and98 are formed of pMOS transistors with their drains and sources shorted,and they are charged by power supply VDD through nMOS transistors 100and 102. Transistors 78, 80, 82 and 84 form the output circuit driving avoltage V_(out) at node 90. The voltage stepper is implemented bytransistors 64, 68, 66 and 70, which form two inverters. Preferably, thedevices operated under the supply voltage VDD are formed of thin oxidetransistors in order to have higher speed, and the devices operated atsupply voltage VDDH are formed of thick oxide transistors to avoiddamage.

As shown in FIG. 4, the gate voltages of transistors 78 and 80 at nodes94 and 88, respectively, are charge pumped by the pMOS capacitors 96 and98. During the first phase, assume the input node 72 is low (0V), thetransistor 100 conducts, and the voltage at node 94 is (VDD−V_(thn)),where V_(thn) is the threshold voltage of the transistors 100 and 102.The capacitor 96 is charged to:Q=(VDD−V _(thn))*C  [Eq. 5]where Q is the charge on capacitor 96 and C is the capacitance.

When input signal voltage V_(in) at node 72 is switched to VDD, thevoltage at node 94 changes to a voltage V₉₄, where V₉₄ is higher than(VDD−V_(thn)), so that the V_(gs) of the transistor 100 is lower thanV_(thn), therefore the transistor 100 cuts off, and it is equivalent toswitch 44 under “open” state (refer to FIG. 3). The charge stored incapacitor 96 is isolated, so that V₉₄ is derived by:(V ₉₄ −V)*C=Q=(VDD−V _(thn))*C  [Eq. 6]and it can be expressed asV ₉₄ =VDD−V _(thn) +V _(in).  [Eq. 7]Since V_(in) equals VDD,V ₉₄=2VDD−V _(thn)  [Eq. 8]When input signal V_(in) is switched back to 0V, the voltage at node 94changes back to (VDD−V_(thn)) again. Therefore, the voltage at node 94switches between (VDD−V_(thn)) and (2VDD−V_(thn)). Similar analysisreveals that the voltage at node 88 is also in a range between(VDD−V_(thn)) and (2VDD−V_(thn)). However, since node 88 is chargepumped by an inverted voltage of the input signal (i.e., the inputvoltage to capacitor 98 that charge pumps node 88 is inverted byinverter pair 64, 68), node 94 and node 88 have opposite phases so thatwhen one is at (VDD−V_(thn)), the other is at (2VDD−V_(thn)).

The function of the charge pump and the voltage stepper can be explainedas follows. When the input signal V_(in) at node 72 switches from 0 toVDD, the node 94 is charge pumped by the pMOS capacitor 96 from(VDD−V_(thn)) to (2VDD−V_(thn)), and the voltage at node 74 is switchedto 0V by the inverter formed by transistors 64 and 68. Note that node 94is connected to the gate of NMOS transistor 78 and that node 74 isconnected to the source of nMOS transistor 78. Therefore, the state ofthe thick oxide nMOS transistor 78 switches from off to on and pullsnode 92 down. The dropping of the voltage at node 92 causes V_(gs) oftransistor 84 to increase. When the gate voltage of transistor 84 ishigher than the threshold voltage, transistor 84 conducts and pulls upthe voltage V_(out) at node 90 to VDDH. Since the V_(gs) of thetransistor 78 is (2VDD−V_(thnd)), which is higher than VDD in the priorart, the drain-source current is higher. It is easier for transistor 78to pull down the voltage at node 92.

At the same time the voltage at node 94 changes from (VDD−V_(thn)) to(2VDD−V_(thn)), the voltage at node 88 changes from (2VDD−V_(thn)) to(VDD−V_(thn)). The output voltage V_(out) is pulled up to VDDH in twostages. During the first stage, it is pushed up to a mid-level voltageV_(step) close to VDD. At the beginning of the first stage, the voltageat node 88 is (2VDD−V_(thn)), and the source voltage at node 76 is 0V.The transistor 80 is on and the drain-source current is high, so thattransistor 80 is a pass gate and its drain voltage follows its sourcevoltage. As time passes, transistor 80's gate voltage at node 88decreases from (2VDD−V_(thn)) to (VDD−V_(thn)), and transistor 80'ssource voltage at node 76 increases from 0V to VDD. Thus the voltageV_(out) at node 90 is pushed to V_(step) by the pass gate 80 until thetransistor 80 is off (which occurs when transistor 80 eventually reachesa gate voltage of (VDD−V_(thn)) and a source voltage of VDD. During thesecond stage, the output voltage V_(out) is pulled up by transistor 84(which is fully on at this point) from V_(step) to VDDH. By the timeV_(out) is pushed to V_(step) and the transistor 80 has cut off,transistor 78 has pulled the voltage at node 92 rather low, so that thetransistor 84 has sufficient drain-source current to further pull upV_(out) to VDDH promptly.

A similar analysis reveals that the same advantageous features arerealized when input node 72 switches from high to low. In this case,node 88 is charge pumped by pMOS capacitor 98 from (VDD−V_(thn)) to(2VDD−V_(thn)) and voltage at node 76 is switched from high to low bythe cascaded inverter pairs 64, 68 and 66, 70. Transistor 80 thusswitches on and pulls output node 90 low (with large drain-sourcecurrent because of the large V_(gs) provided by the charge pump). At thesame time, pMOS capacitor 96 drives node 94 to (VDD−V_(thn)) to turntransistor 78 off. While transistor 78 is turning off, however, node 74(which is tied to the source of transistor 78) is driven high byinverter pair 64, 68. Because transistor 78 also acts as a sourcefollower during switching, the drain of transistor 78, which is at node92, is forced high to an intermediate level (again called V_(step) forsake of convenience, although not necessarily the same intermediatevoltage level to which node 90 was driven during low to high switching).This means that pull-up transistor 82 need only pull node 92 fromV_(step) to VDDH, which in turn quickly turns transistor 84 off.

The preferred embodiment illustrated in FIG. 4 uses one stage of chargepump. With technology advances and core operation voltage furtherdropping, the output voltages of the charge pumps, which are between(VDD−V_(thn)) and (2VDD−V_(thn)) may not be high enough to drive theoutput circuit, and multiple stage charge pumps can be used to push thedriver voltages at nodes 88 and 94 higher. The design of the multiplestage charge pumps are known in the art, and the details are notdiscussed. It is also to be noted that although the voltage stepper usesthe same source supply voltage VDD as the signal driver in the preferredembodiment, in other embodiments, the voltage stepper can be operated ata power supply voltage different from VDD.

The preferred embodiment of the present invention performs correctly ata frequency higher than 1 GHz, compared to about 500 MHz for the priorcircuit illustrated in FIG. 1. FIG. 5 illustrates the voltages as afunction of time of a level shifter made using the preferred embodiment.The level shifter converts a 0.9V core signal to a 3.6V signal and isoperated at a signal speed of 1.25 Gbps. Line 101 is the input signal atnode 72, which has an amplitude of 0.9V. Line 102 is the voltage at node88, and it is charge pumped to between about 0.65V and about 1.33V. Line103 is the output voltage at node 90 that has an amplitude of 3.6V. Itis noted that at a signal speed as high as 1.25 Gbps, the preferredembodiment is still responsive to the rapidly changed signal, and theoutput voltage can be fully lifted to 3.6V before it is switched down.

The preferred embodiment of the present invention has severaladvantages. First, it works for advanced technology (0.13 μm, 90 nm, 65nm and lower) with low core operation voltages. The charge pumpsincrease the driver voltages to a desired level. If the technologyadvances and the core operation voltage further drops, multiple statecharge pumps can further increase the driver voltages. Second, thepreferred embodiments have a wide working frequency range that is fromnear DC to GHz level. The high frequency response is improved byspeeding up the state transition. Third, it has near zero standby powerconsumption when there is no state transition. The result has shown thatfor a lower speed signal, the current drawn from VDD and VDDH are lowerthan about 1 μA during standby state, the peak current at transition isabout 1.5 mA.

Although the present invention and its advantages have been described indetail, it should be understood that various changes, substitutions andalterations can be made herein without departing from the spirit andscope of the invention as defined by the appended claims. Moreover, thescope of the present application is not intended to be limited to theparticular embodiments of the process, machine, manufacture, andcomposition of matter, means, methods and steps described in thespecification. As one of ordinary skill in the art will readilyappreciate from the disclosure of the present invention, processes,machines, manufacture, compositions of matter, means, methods, or steps,presently existing or later to be developed, that perform substantiallythe same function or achieve substantially the same result as thecorresponding embodiments described herein may be utilized according tothe present invention. Accordingly, the appended claims are intended toinclude within their scope such processes, machines, manufacture,compositions of matter, means, methods, or steps.

1. A level shifter comprising: a driver circuit receiving an inputsignal having a first logical pair of voltage levels and boosting saidlogical pair of voltage levels to boosted voltage levels and outputtinga boosted signal and an inverted boosted signal; and an output circuitreceiving the boosted signal and inverted boosted signal and outputtingin response thereto an output signal having a second logical pair ofvoltage levels wherein at least one of said second pair of logicalvoltage levels differs from a corresponding one of said first logicalpair of voltage levels.
 2. The level shifter of claim 1 furthercomprising: a voltage stepper receiving the input signal and driving atleast one node of said output circuit to a voltage corresponding to saidinput signal and driving at least one second node of said output circuitto a voltage corresponding to an inversion of said input signal.
 3. Thelevel shifter of claim 1 wherein said first logical pair of voltagelevels is about 0V and about 1V and said second logical pair of voltagelevels is about 0V and about 3.3V respectively.
 4. The level shifter ofclaim 1 wherein said second logical pair of voltage levels is about 0Vand about 2.5V.
 5. The level shifter of claim 1 wherein said drivercircuit comprises a charge pump.
 6. The level shifter of claim 5 whereinsaid driver circuit comprises: a first charge pump receiving said inputsignal and outputting a boosted signal to a first node of said outputcircuit; and a second charge pump receiving an inverted input signal andoutputting an inverted boosted signal to a second node of said outputcircuit.
 7. The level shifter of claim 6 wherein the first logical pairof voltage levels is VSS and VDD and wherein the boosted voltage levelsare VDD and 2*VDD−V_(thn), where VSS is a lower voltage supply level fora core device, VDD is an upper voltage supply level for a core device,and V_(thn) is a core device threshold voltage.
 8. The level shifter ofclaim 1 wherein the voltage stepper comprises an inverter coupled to theinput signal.
 9. A high speed digital level shifter comprising: a firstpower supply node at a first supply voltage; a second power supply nodeat a second supply voltage wherein the second supply voltage is higherthan the first supply voltage; an input node configured to receive aninput signal; an output node; a signal driver coupled to the first powersupply node and to the input node wherein the signal driver has a firstsignal driver output node configured to output a boosted signalcorresponding to the input signal and a second signal driver output nodeconfigured to output a boosted signal corresponding to an inverted inputsignal; and an output circuit coupled to the second power supply nodeand having a first input coupled to the first signal driver output nodeand a second input coupled to the second signal driver output node, andhaving an output coupled to the output node.
 10. The high speed digitallevel shifter of claim 9 wherein said output circuit comprises: a firstpMOS transistor having a source coupled to the second power supply nodeand a drain coupled to a drain of a first NMOS transistor; a second pMOStransistor having a source coupled to the second power supply node and adrain coupled to a drain of an NMOS transistor; wherein the first nMOStransistor has its drain coupled to the gate of the second pMOStransistor and its gate coupled to the first signal driver output node;and wherein the second nMOS transistor has its drain coupled to the gateof the first pMOS transistor and its gate coupled to the second signaldriver output node.
 11. The high speed digital level shifter of claim 9wherein the signal driver comprises a first charge pump coupled to thefirst signal driver output node, and a second charge pump coupled to thesecond signal driver output node.
 12. The high speed digital levelshifter of claim 9 wherein: the first charge pump comprises a firstcharge transistor having its gate and drain coupled to the first powersupply node, a first capacitor having a first end coupled to the inputnode and a second end coupled to the source of the first chargetransistor and to the gate of the first nMOS transistor; and the secondcharge pump comprises a second charge transistor having its gate anddrain coupled to the first power supply node, a second capacitor havinga first end coupled to the signal driver and a second end coupled to thesource of the second charge transistor and to the gate of the secondnMOS transistor.
 13. The high-speed digital level shifter of claim 12wherein the first and the second capacitors are formed of pMOStransistors having their drains and sources connected.
 14. The highspeed digital level shifter of claim 9 further comprising: a third powersupply node at a third power supply voltage; a signal stepper comprisingthird and fourth pMOS transistors and third and fourth nMOS transistors;wherein the third pMOS transistor has its gate coupled to the input nodeand the signal driver, and its source coupled to the first power supplynode; the fourth pMOS transistor has its source coupled to the thirdpower supply node and its gate coupled to the drain of the third pMOStransistor and the signal driver; the third NMOS transistor has itsdrain coupled to the drain of the third pMOS transistor and its gatecoupled to the input node; and the fourth nMOS transistor has its draincoupled to the drain of the third pMOS transistor, its gate coupled tothe gate of the fourth pMOS transistor and to the junction of the thirdpMOS transistor and the third nMOS transistor.
 15. The high speeddigital level shifter of claim 14 wherein the first power supply voltageequals the third power supply voltage.
 16. An integrated circuitcomprising: a region of core devices operating at a first pair oflogical voltage levels; a region of input/output devices operating asecond pair of logical voltage levels; and a level shifter receiving aninput signal comprising said first pair of logical voltage levels fromsaid region of core devices and outputting an output signal comprisingsaid second pair of logical voltage levels to said region ofinput/output devices, the level shifter comprising: a signal driverconfigured to receive said input signal comprising said first pair oflogical voltage levels and to output a boosted signal comprising a pairof boosted logical voltage levels; and an output circuit coupled to saidsignal driver configured to receive said boosted logical voltage levelsand to output an output signal corresponding to said input signal atsaid second pair of logical voltage levels.
 17. The integrated circuitof claim 16 wherein said level shifter further comprises a voltagestepper circuit coupled to said output circuit and configured to driveat least one node of said output circuit to a logical high voltagelevel.
 18. The integrated circuit of claim 16 wherein said drivercircuit comprises a charge pump.
 19. The integrated circuit of claim 16wherein said first pair of logical voltage levels comprises a logicallow voltage of about VSS and a logic high voltage of about VDD, andwherein said second pair of logical voltage levels comprises a logicallow voltage of about VSS and a logical high voltage of about VDDH,wherein VDDH is greater than VDD.
 20. The integrated circuit of claim 19wherein VDD is about 0.9V to about 1.0V and VDDH is about 2.5V to about3.3V.
 21. A method of level shifting a signal comprising: boosting aninput signal to a driver signal having voltage levels higher than thevoltage levels of the input signal; and driving an output circuit withthe driver signal to generate an output signal having an amplitude of ahigh power supply voltage, wherein the output circuit is operated at thehigher power supply voltage.
 22. The method of claim 21 furthercomprising the steps of: stepping up the output voltage to a stepvoltage; and pulling up the output voltage from the step voltage to thehigher power supply voltage.
 23. The method of claim 22 wherein the stepof stepping up the output voltage is performed by a circuit comprisingan inverter.
 24. The method of claim 21 wherein the step of driving upthe input voltage is performed by a circuit comprising a charge pump.